ID:13826 VHDL Syntax error at <location>: experienced unexpected end-of-file

CAUSE: In a VHDL Design File (.vhd) at the specified location, Quartus Prime Integrated Synthesis encountered an unexpected end-of-file before it fully parsed the VHDL Design File.

ACTION: Make sure you did not omit semicolons, keywords, or other necessary delimiters or text from the VHDL Design File.