ID:13236 Verilog HDL unsupported feature error at file "<name>" (line <number>): can't synthesize tran, rtran, or tranif bidirectional pass gate primitive

CAUSE: In a Verilog Design File (.v) at the specified location, you instantiated a tran, rtran, or tranif bidirectional pass gate primitive. However, Quartus Prime Integrated Synthesis cannot synthesize bidirectional pass gate primitives.

ACTION: Edit the design to remove all bidirectional pass gate primitives. If you want, you can replace the bidirectional pass gate primitives with behavioral models of the basic gates in the design, or you can rewrite the design in a behavioral style.