ID:18320 Bidirectional port "<name>" directly or indirectly feeds itself.

CAUSE: In a Verilog Design File (.v) or a VHDL Design File (.vhd), you declared the specified bidirectional port. Later, you made one or more value assignments to the port. However, these assignments indirectly or directly assign the port to itself, which results in an unsupported loop in your design.

ACTION: Examine the assignments to the specified bidirectional port. Remove any assignments that create a loop.