Output Enable Pin Delay logic option

A logic option that specifies the propagation delay to the output enable pin from internal logic or the output enable register implemented in an I/O cell. Use this advanced option after you compile a project, check the I/O timing, and determine that the timing is unsatisfactory.

This option is useful for fine-tuning the I/O timing of your design and meeting tCO requirements.

This option must be assigned to an output or bidirectional pin or it is ignored.

For detailed information on this logic option, refer to the device family data sheet available from the Literature section of the Altera website .

This option is available for supported device (Arria^® II GX, and Cyclone^® IV) families