TMC-20215: Buses with Incoming Paths Failing Setup Analysis with Multipliers Implemented in Logic
Description
Violations of this rule indicate buses that are endpoints of setup-failing timing paths that contain multipliers implemented in soft logic.
The Compiler implements multipliers in soft logic if, for example, the DSP blocks in the device are highly used. Multipliers in soft logic usually run slower than multipliers in hardened DSP blocks.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| maximum_setup_slack | Reports a violation for timing paths that have a setup slack below the value of this parameter. | double | 0.0 | ||
| to_clock_filter | Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. | string | * | ||
| minimum_number_of_adders | Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. | integer | 3 | ||
| minimum_number_of_soft_mult_chains | Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. | integer | 2 |
Recommendation
Convert the multipliers into DSP blocks or select a device with more DSP blocks. Apply the 'multstyle' RTL pragma with the value of 'dsp' to force a multiplier to be implemented in DSP blocks.
Severity
Medium
Tags
| Tag | Description |
|---|---|
| logic-levels | Design rule checks which flag potentially problematic amounts of logic on a timing path. |
| dsp | Design rule checks related to DSP blocks inside the FPGA fabric. |
Device Family
- Intel®Stratix® 10
- Intel Agilex®
- Intel®Arria® 10
- Intel®Cyclone® 10 GX