TMC-20209: Paths Failing Setup Analysis with High Routing Delay due to Congestion
Description
Violations of this rule identify paths that fail setup analysis adversely affected by routing congestion. If the demand for fast routing resources exceeds the available resources in a region of the device, some signals, while routable, may not have enough fast resources allocated to meet timing constraints.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| maximum_setup_slack | Reports a violation for timing paths that have a setup slack below the value of this parameter. | double | 0.0 | ||
| to_clock_filter | Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. | string | * | ||
| minimum_number_of_adders | Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. | integer | 3 | ||
| minimum_number_of_soft_mult_chains | Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. | integer | 2 |
Recommendation
Use the Report Routing Utilization task in the Chip Planner to identify zones with lack of routing resources. This command helps you to make design changes to meet routing congestion design requirements. Refer to Viewing Routing Congestion in Intel Quartus Prime Pro Edition User Guide: Design Optimization for more information.
Severity
Medium
Tags
| Tag | Description |
|---|---|
| route | Design rule checks which pertain to the Compiler's Route stage. |
Device Family
- Intel®Stratix® 10
- Intel Agilex®
- Intel®Arria® 10
- Intel®Cyclone® 10 GX