TMC-20203: Paths Failing Setup Analysis with High Fabric Interconnect Delay
Description
Violations of this rule identify paths with a "fabric-IC-only slack" below the maximum_setup_slack threshold parameter.
Timing paths may fail setup analysis without any delay contributions from cell delay, local interconnect delay, or clock skew. If those components are removed from the overall slack, the remaining slack is the path's fabric interconnect delay, as well as the combination of the clock relationship, endpoint microparameters, SDC constraints, and other such requirements. These requirements together constitute a path's fabric-IC-only slack. A negative fabric-IC-only slack implies that you must reduce the fabric interconnect on a path or its requirements.
For example, consider a path with a combined μtco, μtsu, and fabric interconnect delay that together exceeds the target clock period. Such a path is likely to fail setup analysis, and as such its fabric-IC-only slack is negative. Reduce the fabric interconnect on a path or relax its setup requirements.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| maximum_setup_slack | Reports a violation for timing paths that have a setup slack below the value of this parameter. | double | 0.0 | ||
| to_clock_filter | Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. | string | * | ||
| minimum_number_of_adders | Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. | integer | 3 | ||
| minimum_number_of_soft_mult_chains | Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. | integer | 2 |
Recommendation
Restructure the path to increase its fabric-IC-only slack:
- Decrease the hold requirement on one or more of its connections. A connection may be shared across multiple timing paths.
- Adjust placement constraints to reduce the physical distance between each node on the path.
- Reduce congestion in the nearby area.
- Add pipeline registers to distribute long-routed signals over several clock cycles.
- Adjust SDC constraints to relax the path's setup constraint.
- If the path's endpoints involve DSP, RAM, or I/O blocks, ensure that those blocks are sufficiently registered.
- If the launch and latch clocks are different, ensure their relationship is properly constrained.
Severity
Medium
Tags
| Tag | Description |
|---|---|
| intrinsic-margin | Design rule checks which use the Intrinsic Margin metric (slack ignoring cell delay, IC delay and clock skew) to diagnose potential timing issues on failing paths. |
Device Family
- Intel®Stratix® 10
- Intel Agilex®
- Intel®Arria® 10
- Intel®Cyclone® 10 GX