LNT-30010: Nets Driving both Reset and Clock Enable Signals
Description
Violations of this rule identify signals that drive both synchronous (or asynchronous) reset and clock enable signals. It is uncommon to intentionally mix reset and clock enable signals.
Recommendation
Verify that mixing of synchronous reset and clock enable signals is intended. If it is unintentional, restructure the RTL. If it is intentional, waive the violations or duplicate the driver to isolate the reset fanouts from the clock enable fanouts.
Severity
Low
Tags
| Tag | Description |
|---|---|
| reset-usage | Design rule checks related to safe resets or appropriate use of reset modes. |
Device Family
- Intel®Arria® 10
- Intel Agilex®
- Intel®Stratix® 10