D4 Delay (DQS Delay Chain) logic option

A logic option that specifies the propagation delay from the I/O buffer to the input register for the D4 delay cell. This is an advanced option; use this option only after compiling your project, checking I/O timing, and determining that timing is unsatisfactory. This option is ignored if it is applied to anything other than an input or bidirectional pin.

This option is available for supported device (Arria^® II GZ, Stratix^® III, Stratix^® IV, and Stratix^® V) families.