Optimize Design for Metastability logic option

A logic option that improves the reliability of the design by increasing its Mean Time Between Failures (MTBF). The design MTBF is estimated from chains of registers that synchronize data transferred between unrelated clock domains. Each chain of registers has an associated MTBF that has an exponential dependency on the settling time of the chain. The settling time is computed as the sum of the output setup slack of each register in the chain. This option directs the Fitter to increase the output setup slack of the synchronizer registers in the chain, which can exponentially increase the design MTBF. For this option to correctly optimize the design for metastability, you must use the Timing Analyzer for timing analysis.

This option is a project wide-option. This option is available for supported device (Arria^® II, Cyclone^® III, Cyclone^® IV, Stratix^® III, Stratix^® IV, and Stratix^® V) families.