Create Debugging Nodes for IP Cores logic option

A logic option that make certain nodes, such as important registers; pins; and state machines, visible to Analysis & Synthesis for all the Intel^® FPGA IP functions in a design. When the nodes of a Intel^® FPGA IP function are visible, you can more effectively debug the megafunction, particularly when using the megafunction with the Signal Tap Logic Analyzer. You can use the Signal Tap Logic Analyzer filters in the Node Finder to display the nodes discovered by Analysis & Synthesis. When the debugging nodes are visible, Analysis & Synthesis can change the fMAX and number of logic cells in Intel^® FPGA IP functions