About Using the Synplify Software with the Intel® Quartus® Prime Software
You can use the Synopsys® Synplify design entry/synthesis tool to create, synthesize, and optimize a project and then generate a Verilog Quartus Mapping File (.vqm) Definition for compilation in the Intel® Quartus® Prime software. The following topics describe the typical flow with the Synplify software and the Intel® Quartus® Prime software:
- Set up the Synplify working environment
- Create a design for use with the Synplify software
- Set up a project with the Synplify software
- Assign design constraints with the Synplify software
- Generate Verilog Quartus Mapping Files with the Synplify software
- Analyze design results with the Synplify software
You can use Intel-provided Intel® FPGA IP in the Synplify software by using the IP Catalog to create custom Intel® FPGA IP variations that are based on Intel-provided Intel® FPGA IP. Refer to the following topics for information on how to use specific Intel® FPGA IP:
- Creating and Instantiating a VHDL Function for Use with the Synplify Software
- Creating and Instantiating a Verilog HDL Function for Use with the Synplify Software
You can use the same procedures and principles with similar Intel® FPGA IP in other designs.