Library Mapping File (.lmf) Definition

An ASCII text file (with the extension .lmf) used to map cells in EDIF Input Files (.edf) and Verilog Quartus Mapping Files (.vqm), components in VHDL Design (.vhd) File, or modules in Verilog Design (.v) File to corresponding Intel^® Quartus^® Prime logic functions.

LMFs allow the Compiler to substitute Intel^® Quartus^® Prime logic functions for the cells in EDIF Input Files, VHDL Design Files, Verilog Design Files, and VQM Files. LMFs also eliminate the need for the Compiler to extract the information on those cells or functions and allow the Compiler to substitute Intel^® Quartus^® Prime logic functions for non-Intel^® Quartus^® Prime logic functions. The logic function mappings in Intel-provided LMFs allow you to take advantage of family-specific macrofunctions.

All cells in EDIF Input Files and VQM Files, and some of the functions in VHDL Design Files and Verilog Design Files must be mapped to Intel logic functions in an LMF so that the Compiler can interpret them.

Note: If a VHDL Design File contains VHDL primitives that have Component Declarations in the maxplus2 package (which is in the \quartus\libraries\vhdl\altera directory), you must specify maxplus2.lmf as the LMF for the VHDL Design File.

LMFs for EDIF Input Files and VQM Files are specified as Compiler input files when you specify an LMF in the File name box in the Design Entry & Synthesis page of the Settings dialog box (Assignments menu). LMFs for VHDL Design Files are specified in the VHDL Input page of the Settings dialog box (Assignments menu), and LMFs for Verilog Design Files are specified in the Verilog HDL Input page of the Settings dialog box.

You can use one of the following Intel-provided LMFs generated by industry-standard EDA tools:

Software	Library Mapping File
Design Compiler	altsyn.lmf
DK Design Suite	agility.lmf
LeonardoSpectrum	mentor.lmf
Precision RTL Synthesis	mentor.lmf
Synplify	synplcty.lmf
ViewDraw	vwl_bas.lmf

You can also create new custom LMFs for EDIF Input Files, VHDL Design Files, and Verilog HDL Design Files.