Auxiliary Transmit (ATX) PLL Definition

A feature available in Stratix^® IV GT and Stratix^® IV GX devices that employs a phase-locked loop (PLL). The Auxiliary Transmit (ATX) PLL produces very low jitter high frequency clocks and is designed to operate in a narrow frequency range. The ATX PLL distributes high-speed clocks through the clock divider, which also produces low-speed parallel clocks. The ATX PLL allows you to clock and bond all of the transceiver channels with a single PLL.

You can take advantage of the ATX PLL with the altgx Intel^® FPGA IP.