Speed Optimization Technique for Clock Domains logic option

A logic option that specifies that all combinational logic in the given clock domain, or between the given clock domains should be mapped with an optimization technique speed.

When this option is set on a particular clock, all the logic in this clock domain are synthesized for speed. The remainder of the device is synthesized with the project-wide settings specified in the Optimization Technique option. The Speed Optimization Technique for Clock Domains option can also be set from a "clock a" to a "clock b", in which case the logic on the paths from the registers on clock domain a to registers in clock domain b are synthesized for speed. The advantage of using this option over the Optimization Technique option with a speed setting is that the area penalty is smaller because a smaller part of the device is mapped for speed. This may also have a positive effect on the clock speed.

This option is useful if you have one or more clock domains that do not meet timing requirements. When there are failing paths within a clock domain, the option can be set on that clock domain. When there are failing paths between clock domains, the option can be set from one clock domain to the other clock domain.

This option must be assigned to either one or two clock signals or it is ignored. Warnings are given for ignored options.