Auto Shift Register Recognition logic option

Allows the Compiler to replace groups of shift registers of the same length with the altshift_taps Intel^® FPGA IP. The shift registers must all use the same clock and clock enable signals, must not have any other secondary signals, and must have equally spaced taps that are at least three registers apart.

This option is useful for finding areas of the design that allow a more efficient implementation, and as a result, minimizing the area and maximizing the speed of the design.

The Compiler ignores this option if assigned to other than a design entity or node.