RES-30133: Embedded Memory Blocks with Initialized Content That Might be Modified Before the FPGA Enters User Mode

Description

Violations of this rule identify embedded memory blocks with initialized content that might be modified before the FPGA enters user mode.

FPGA programming has a configuration stage that programs the FPGA logic and routing followed by an unfreeze stage that ends with the FPGA entering user mode for normal operation. To avoid the complexity of unfreeze, Intel recommends that embedded memories with initialized content (such as MIF or HEX initialization) must be ROMs and not RAMs because if a RAM block unfreezes before the write logic is ready, then the RAM content might get modified before user mode starts. In the event that one must use RAMs with initial content, then careful design practices must be followed to protect the RAM content in the unfreeze stage. This design rule performs a sanity check for these design practices. However it does not guarantee that the logic is actually done correctly. Refer to Implementing Clock Enable for On-Chip Memories with Initialized Contents in Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration for more information.

This rule checks that registers driving the write enable or clock enable port of these embedded memories explicitly power up to low. This is a necessary but not sufficient condition for preventing modification of the RAM block before user mode starts. If the write enable or clock enable port is driven by non-trivial combinational logic, this rule will still trigger because such design practice is fragile for the unfreeze process; the user can waive a violation if they are confident on such design practice.

Note: This rule does not apply for Partial Reconfiguration partitions. For embedded memory in Partial Reconfiguration partitions, refer to techniques in Implementing Clock Enable for On-Chip Memories with Initialized Contents in Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration.

Parameters

Name	Description	Type	Default Value	Min Value	Max Value
exclude_ram_blocks_without_mif	Exclude embedded memory blocks that do not specify memory initialization files	bool	1

Recommendation

First, we recommend switching to a ROM to avoid the complexity of unfreeze. If this is not possible, explicitly set the power-up value of the register feeding write enable or clock enable port of the RAM block to low. We also recommend checking that the reset chain of the register feeding write enable or clock enable port is held in reset throughout the unfreeze process, and that initial conditions on that reset chain be correctly set (this rule does not check this reset logic).

Severity

Medium

Tag	Description
ram	Design rule checks related to M20k blocks inside the FPGA fabric.
reset-usage	Design rule checks related to safe resets or appropriate use of reset modes.

Device Family