Intel^® FPGA IP

Intel^® FPGA IP List

Displays a list of Pin Planner"“ compatible Intel^® FPGA IP that you created or imported into the design.

Intel^® FPGA IP Table

• Intel^® FPGA IP—Displays the name of the Intel^® FPGA IP.
• Instance—Displays the name you assigned to the Intel^® FPGA IP instance.
• Port Name—Displays the names of the ports contained in the Intel^® FPGA IP. Buses are displayed as a group.
• Direction—Displays whether the port is an input, output, or bidirectional port.
• Type—Specifies whether the port is internal or external. Nodes assigned to internal ports cannot be assigned to device pins. If you change the port type, all ports connected by the same node are changed likewise. Nodes assigned to internal ports are not displayed in the Groups and All Pins lists, but do appear in the generated top-level design file as virtual pins. If you change all the ports in a Intel^® FPGA IP group to internal ports, they do not display in the Groups list. Nodes assigned to external ports are assigned to device pins.
• Node Name—Displays the node name associated with the port. You can change the node name to connect multiple ports in different groups to a single node.