To compile libraries and design files with the QuestSim GUI

  1. If you have not already done so, set up a project with the QuestaSim software.
  2. On the Compile menu, click Compile.
  3. In the Library list of the Compile HDL Source Files dialog box, select the work library.
  4. In the Files of Type list, select All Files (*.*), and in the Look in list, select the appropriate simulation model library.
    Note: For VHDL-93 compliant designs, turn on Use 1993 Language Syntax under Default Options.
  5. Click Compile.
  6. Repeat steps 2 to 4 for the Verilog HDL or VHDL Output File and the test bench file (if you use one) that instantiates the Verilog HDL or VHDL Output File.
    Important: Important: If your design contains the alt2gxb Intel® FPGA IP, refer to the appropriate Intel® FPGA IP topic for required settings.
  7. Click Done.