Enable SDO Generation for Power Analysis

Directs the EDA Netlist Writer to generate a Standard Delay Output (.sdo) file that includes back-annotation of delays for a design's netlist for use during simulation in ModelSim^®. Although the .sdo only contains delay estimates and imprecise timing information, including the .sdo in simulation results in a more accurate output .vcd for power analysis.

Note: The EDA Netlist Writer currently supports .sdo file generation only for Verilog ModelSim^® simulation of Intel^® Stratix^® 10 designs.