Show "X" on Timing Violation logic option

A logic option that shows timing violations during a simulation. This option shows an "X" state or valid data at the output of registers when a timing violation occurs.

This option is useful if you want setup or hold register violations to force an "X" state on registers during simulations. The dcfifo Intel^® FPGA IP automatically turns off this option on internal synchronization registers that cross clock domains. This prevents you from seeing false timing violations from dcfifo Intel^® FPGA IP when you enable this option globally.

This option must be assigned to a register or it is ignored.