AHDL Function Prototype (port name and order also apply to Verilog HDL)
The following AHDL function prototype is located in the AHDL Include File (.inc) Definitioncsfifo.inc located in the <Intel® Quartus® Prime installation directory>\libraries\megafunctions directory.
FUNCTION csfifo( data[lpm_width-1..0], wreq, rreq, clock, clockx2, clr, sclr, threshlevel[CEIL(LOG2(LPM_NUMWORDS))-1..0] ) WITH( LPM_WIDTH, LPM_NUMWORDS, LPM_SHOWAHEAD, UNDERFLOW_CHECKING, OVERFLOW_CHECKING, ALLOW_RWCYCLE_WHEN_FULL ) RETURNS ( q[(lpm_width)-(1)..0], threshold, empty, full, usedw[CEIL(LOG2(LPM_NUMWORDS))-1..0] );