I/O standards Definition

Standards that uniquely define the input and output (VCCIO) voltage, reference VREF voltage (if applicable), and the types of input and output buffers used for I/O pins.

The following table lists I/O standards and the corresponding Intel® Quartus® Prime Settings File (.qsf) settings keyword.

To see the standards that a device family supports, refer to the device datasheet.

I/O Standard QSF Keyword
1.2-V

"1.2 V",

"1.2V",

"1.2-V"

1.2-V HSTL Class I and II

"1.2- V HSTL",

"1.2- V HSTL Class I",

"1.2- V HSTL Class II"

1.2-V HSUL "1.2-V HSUL"
1.2-VPCML "1.2- V PCML"
1.4-V PCML "1.4-V PCML"
1.5-V

"1.5 V", "1.5V",

"1.5- V"

1.5-VHSTL Class I

"1.5- V HSTL Class I",

"HSTL Class I"

1.5-VHSTL Class II

"1.5- V HSTL Class II",

"HSTL Class II"

1.5-VPCML "1.5- V PCML"
1.8V

"1.8 V",

"1.8V",

"1.8- V"

1.8-V HSTL Class I and II

"1.8- V HSTL Class I",

"1.8- V HSTL Class II"

2.5-V

"2.5 V", "2.5V",

"2.5- V"

2.5 V LVDS LVDS
2.5-V PCML "2.5-V PCML"
2.5-V Schmitt Trigger Input "2.5V Schmitt Trigger Input"
3.0-V LVCMOS

"3.0-V LVCMOS",

"3.0V LVCMOS"

3.0-V LVTTL

"3.0-V LVTTL",

"3.0V LVTTL"

3.0-VPCI "3.0- V PCI"
3.0-VPCI-X

"3.0- V PCI- X",

"3.0- V PCI X"

3.3-V LVCMOS

"3.3-V LVCMOS",

"3.3V LVCMOS",

"LVCMOS"

3.3-V LVTTL "LVTTL"
3.3-VPCI "3.3- V PCI"
3.3-VPCI-X

"3.3-V PCI-X",

"3.3- V PCI X"

3.3-VPCML

"3.3- V PCML",

"PCML",

"CML"

3.3-V Schmitt Trigger Input "3.3V Schmitt Trigger Input"
Bus LVDS "Bus LVDS"
Differential I/O standards  
2.5 V LVDS LVDS
Differential 1.2-V HSTL Class I and II

"Differential 1.2- V HSTL",

"Differential 1.2- V HSTL Class I",

"Differential 1.2- V HSTL Class II"

Differential 1.2-V HSUL "Differential 1.2-V HSUL"
Differential 1.2-V SSTL "Differential 1.2-V SSTL"
Differential 1.25-V SSTL "Differential 1.25-V SSTL"
Differential 1.35-V SSTL "Differential 1.35-V SSTL"
Differential 1.5-V HSTL Class I

"Differential HSTL",

"Differential 1.5- V HSTL",

"Differential 1.5- V HSTL Class I"

Differential 1.5-V HSTL Class II

"Differential HSTL Class II",

"Differential 1.5- V HSTL Class II"

Differential 1.5-V SSTL "Differential 1.5-V SSTL"
Differential 1.5-V SSTL ClassIand II

"Differential 1.5-V SSTL Class I",

"Differential 1.5-V SSTL Class II"

Differential 1.8-V HSTL ClassIand II

"Differential 1.8- V HSTL Class I",

"Differential 1.8- V HSTL Class II"

Differential 1.8-V SSTL ClassIand II

"Differential 1.8- V SSTL Class I",

"Differential 1.8- V SSTL Class II"

Differential 2.5-V SSTL ClassIand II

"Differential 2.5- V SSTL Class I"

"Differential 2.5- V SSTL Class II"

Differential LVPECL "Differential LVPECL"
Differential SSTL-2 ClassI "Differential SSTL- 2"
Differential SSTL-2 ClassII "Differential SSTL- 2 Class II"
HCSL "HCSL"
LVDS "LVDS"
LVDS_E_1R "LVDS_E_1R"
LVDS_E_3R "LVDS_E_3R"
LVPECL LVEPCL
mini-LVDS "mini-LVDS"
mini-LVDS _E_R "mini-LVDS",
mini-LVDS _E_3R "mini-LVDS",
RSDS "RSDS"
RSDS_E_1R "RSDS_E_1R"
RSDS_E_3R "RSDS_E_3R"
Schmitt Trigger Input

"2.5V Schmitt Trigger Input",

"3.3V Schmitt Trigger Input"

SSTL-12 "SSTL-12"
SSTL-125 Class I "SSTL-125"
SSTL-135 Class I "SSTL-135"
SSTL-15 "SSTL-15"
SSTL-15 Class I "SSTL- 15 Class I"
SSTL-15 Class II "SSTL- 15 Class II"
SSTL-18 Class I and II

"SSTL- 18 Class I",

"SSTL- 18 Class II"

SSTL-2 Class I and II

"SSTL- 2 Class I",

"SSTL- 2 Class II"

POD12 "1.2-V POD
Differential POD12 "Differential 1.2-V POD
High Speed Differential "High Speed Differential I/O"
PPDS "PPDS"
PPDS_E_3R "PPDS_E_3R"
SLVS "SLVS"
mini-LVDS_E_1R "mini-LVDS_E_1R"
mini-LVDS_E_3R "mini-LVDS_E_3R
CML "CURRENT MODE LOGIC (CML)"
1.5-V Schmitt Trigger Input "1.5V Schmitt Trigger Input"
1.8-V Schmitt Trigger Input "1.8V Schmitt Trigger Input"
HiSpi "HISPI"
Sub-LVDS "SUB-LVDS"
TMDS TMDS
Note: For more information about I/O standard support for specific device families, refer to the FPGA device documentation for your device.