Snapshot Viewer Commands
You can access these commands by clicking the Snapshot Viewer icon in
the Compilation Dashboard. You can run the Snapshot Viewer to assist with timing closure
and design analysis after running the Plan, Place, or Route stages of the Fitter. The
Snapshot Viewer allows you to run various analysis tasks from the Flow Navigator to achieve faster timing closure and
maximize design performance.
Design Task | Available at Snapshot | Snapshot Viewer Commands |
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Timing Closure—Analyze Failing Paths | Planned, Placed, Routed, Finalized |
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Placed, Routed, Finalized |
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Timing Closure—Analyze
Clocking This task is available only for Intel® Stratix® 10 devices. |
Placed, Finalized | Show Global Clock Visualization—loads the Global Signal Visualization report for the snapshot that allows you to visualize clock sector utilization. |
Timing Closure—Analyze High Fanout Nets | Placed, Routed, Finalized |
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Timing Closure—Validate Constraints | Planned | Timing Exceptions—displays the Timing Exceptions Results report that identifies timing paths with hold or removal slack exceeding threshold. |
Planned, Placed, Finalized | Check Unregistered Ports—displays the Check Unregistered Ports Results report that identifies unregistered partition inputs and paths. | |
Timing Closure—Analyze Congestion | Placed, Routed, Finalized | Show Logic Lock Regions with Congestion Heat Map—the Chip Planner displays the Logic Lock regions in a congestion heat map for further analysis. |