Optimization Mode
The following options direct the focus of Compiler optimization efforts during synthesis. Specify a Balanced strategy, or optimize for Performance, Area, Routability, Power, or Compile Time. The Compiler targets the optimization goal you specify.
Optimization Mode |
Description |
---|---|
Balanced (normal flow) |
The Compiler optimizes synthesis for balanced implementation that respects timing constraints. |
High performance effort |
The Compiler increases the timing optimization effort during placement and routing, and enables timing-related Physical Synthesis optimizations (per register optimization settings). Each additional optimization can increase compilation time. |
High performance with maximum placement effort | Enables the same Compiler optimizations as High performance effort, with additional placement optimization effort. |
High performance with aggressive power effort | Enables the same Compiler optimizations as High performance effort, while performing additional optimizations to reduce dynamic-power. |
Superior performance | Enables the same Compiler optimizations as High performance effort, and adds more optimizations during Analysis & Synthesis to maximize design performance with a potential increase to logic area. If design utilization is already very high, this option may lead to difficulty in fitting, which can also negatively affect overall optimization quality. |
Superior performance with maximum placement effort | Enables the same Compiler optimizations as Superior performance, with additional placement optimization effort. |
Aggressive Area |
The Compiler makes aggressive effort to reduce the device area required to implement the design at the potential expense of design performance. |
High placement routability effort | The Compiler makes high effort to route the design at the potential expense of design area, performance, and compilation time. The Compiler spends additional time reducing routing utilization, which can improve routability and also saves dynamic power. |
High packing routability effort | The Compiler makes high effort to route the design at the potential expense of design area, performance, and compilation time. The Compiler spends additional time packing registers, which can improve routability and also saves dynamic power. |
Optimize netlist for routability | The Compiler implements netlist modifications to increase routability at the possible expense of performance. |
Aggressive power |
Makes aggressive effort to optimize synthesis for low power. The Compiler further reduces the routing usage of signals with the highest specified or estimated toggle rates, saving additional dynamic power but potentially affecting performance. |
Aggressive Compile Time |
Reduces the compile time required to implement the design with reduced effort and fewer performance optimizations. This option also disables some detailed reporting functions. Turning on Aggressive Compile Time enables Intel® Quartus® Prime Settings File (.qsf) settings which cannot be overridden by other .qsf settings. |
Fast Functional Test |
Reduces the compile time required to implement the design with reduced efforts and limits timing optimizations to only those for hold requirements. This option also disables some detailed reporting functions. Turning on Fast Functional Test enables Intel® Quartus® Prime Settings File (.qsf) settings which cannot be overridden by other .qsf settings. |