Constraints Menu Create Clock Dialog Box (create_clock) You access the functions of this dialog box by clicking Constraints > Create Clock in the Timing Analyzer, or with the create_clock Synopsys® Design Constraints (SDC) command. Create Generated Clock Dialog Box (create_generated_clock) You access this dialog box by clicking Constraints > Create Generated Clock in the Timing Analyzer, or with the create_generated_clock Synopsys® Design Constraints (SDC) command. Set Clock Latency Dialog Box (set_clock_latency) You access this dialog box by clicking Constraints > Set Clock Latency in the Timing Analyzer, or with the set_clock_latency Synopsys® Design Constraints (SDC) command. Set Clock Uncertainty Dialog Box (set_clock_uncertainty) You access this dialog box by clicking Constraints > Set Clock Uncertainty in the Timing Analyzer, or with the set_clock_uncertainty Synopsys® Design Constraints (SDC) command. Set Clock Groups Dialog Box (set_clock_groups) You access this dialog box by clicking Constraints > Set Clock Groups in the Timing Analyzer. Remove Clock Dialog Box (remove_clock) You access this dialog box by clicking Constraints > Remove Clock of the Timing Analyzer, or with the remove_clock Synopsys® Design Constraints (SDC) command described in the SDC syntax reference. This constraint applies only to Timing Analyzer analysis. Set Input Delay Dialog Box (set_input_delay) You access this dialog box by clicking Constraints > Set Input Delay in the Timing Analyzer, or with the set_input_delay Synopsys® Design Constraints (SDC) command. Set Output Delay Dialog Box (set_output_delay) You access this dialog box by clicking Constraints > Set Output Delay in the Timing Analyzer, or with the set_output_delay Synopsys® Design Constraints (SDC) command. Derive PLL Clocks (derive_pll_clocks) You access the functions of this dialog box by clicking Timing Analyzer's Constraints > Derive PLL Clocks, or with the derive_pll_clocks Synopsys® Design Constraints (SDC) command. Derive Clock Uncertainty (derive_clock_uncertainty) You access the functions of this dialog box by clicking Timing Analyzer's Constraints > Derive Clock Uncertainty, or with the derive_clock_uncertainty Synopsys® Design Constraints (SDC) command. Set False Path Dialog Box (set_false_path) You access this dialog box by clicking Constraints > Set False Path in the Timing Analyzer, or with the set_false_path Synopsys® Design Constraints (SDC) command described in the SDC syntax reference. A variation of this command is available by selecting a path in the Clock Transfers report and clicking Set False Paths Between Clock Domains. Set Multicycle Path Dialog Box (set_multicycle_path) You access this dialog box by clicking Constraints > Set Multicycle Path in the Timing Analyzer, or with the set_multicycle_path Synopsys® Design Constraints (SDC) command. Set Maximum Delay Dialog Box (set_max_delay) You access this dialog box by clicking Constraints > Set Maximum Delay in the Timing Analyzer, or with the set_max_delay Synopsys® Design Constraints (SDC) command. Set Minimum Delay Dialog Box (set_min_delay) You access this dialog box by clicking Constraints > Set Minimum Delay in the Timing Analyzer, or with the set_min_delay Synopsys® Design Constraints (SDC) command. Reset Design Command (Timing Analyzer) You access this command by double-clicking Constraints > Reset Design in the Timing Analyzer.