Board-level signal integrity analysis

Allows you to select HSPICE to generate HSPICE Simulation Deck File (.sp) Definition or IBIS to generate IBIS Output File (.ibs) Definition.

Note: HSPICE model generation is available for supported device families. Refer to the SPICE models section of the Signal and Power Integrity Support Center in the Intel FPGA website.

Scripting Information

Keyword: eda_board_design_signal_integrity_tool

Settings: "IBIS (Signal Integrity)" | "HSPICE (Signal Integrity)" |"<None>*"

*default

IBIS model generation is fully supported for all devices supported by the Intel^® Quartus^® Prime software. For additional IBIS model device support and support files, refer to the IBIS models section of the Signal Integrity section on the Altera website.

You can turn on Enable model selector in supported signal integrity analysis tools.

Scripting Information

Keyword: eda_ibis_model_selector

Settings: on | off*

*default

You can turn on Print per pin RLC package model with mutual coupling to generate an IBIS Output File (.ibs) with mutual coupling.

Scripting Information

Keyword: eda_ibis_mutual_coupling

Settings: on | off*

*default