Auto Gated Clock Conversion logic option

A logic option that automatically converts gated clocks in the design to use clock enable pins if clock enable pins are not used in the original design. Clock gating logic can contain AND, OR, MUX, and NOT gates. Turning on this option may increase memory use and overall run time.

This option is useful for prototyping ASIC designs on FPGA devices since gated clocks are not ideal for the FPGA architecture. For this option to correctly convert gated clocks to equivalent logic, you must use the Timing Analyzer for timing analysis, and you must define all base clocks in Synopsys^® Design Constraints (SDC) format.

You can use this option as a project-wide option, or assign it to a design entity. This option is available for supported device (Arria^® series, Cyclone^® III, Cyclone^® IV, Stratix^® III, Stratix^® IV, and Stratix^® V) families.