Input Ports
Port Name |
Required |
Description |
Comments |
|---|---|---|---|
data[][] |
Yes |
Data input to the AND gate. |
Input port LPM_SIZE x LPM_WIDTH wide. Two-dimensional bus ports are not supported in Verilog HDL. |
Port Name |
Required |
Description |
Comments |
|---|---|---|---|
data[][] |
Yes |
Data input to the AND gate. |
Input port LPM_SIZE x LPM_WIDTH wide. Two-dimensional bus ports are not supported in Verilog HDL. |