Truth Table/Functionality

Read Operations
addr[]	di[]	nread	nbusy	Function
valid byte	don't care	falling edge	1 -> 0	Reads data from the address indicated by the `addr[]` port and shifts the data to the `do[]` port. You must wait until the `data_valid` signal goes high before attempting to get the data value from the `do[]` port. The `nbusy` signal is low while the `altufm_parallel` Intel^® FPGA IP reads the instruction and goes high once the `altufm_parallel` Intel^® FPGA IP completes the read instruction and data is valid on the `do[]` port. Before adding another instruction, wait until the `nbusy` signal goes high.
don't care	don't care	rising edge/constant	don't care	No change.

Write Operations
addr[]	di[]	nwrite	nbusy	Function
valid byte	valid byte	falling edge	1 -> 0	Programs the `di[]` port value into the memory location pointed to by the `addr[]` port. The `nbusy` signal remains low while the `altufm_parallel` Intel^® FPGA IP performs the write operation. Before adding another instruction, wait until the `nbusy` signal goes high.
don't care	don't care	rising edge/constant	don't care	No change.

Erase Operations
addr[]	nerase[]	nbusy	Function
valid byte	falling edge	1 -> 0	Erases the memory sector indicated by the MSB of the `addr[]` port. A MSB with a value of `0` means that sector 0 is erased. A MSB with a value of `1` means that sector 1 is erased. The `nbusy` signal remains low while the UFM sector is erased. Before adding another instruction, wait until the `nbusy` signal goes high.
don't care	rising or constant	don't care	No change.