TMC-20213: Paths Failing Setup Analysis with Locally Routed Clock
Description
Violation of this rule identifies setup failing paths that use local routing resources in their clock path. As compared to local routing resources global resources have much less min max spread and consquently reduce the amount of clock skew.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| maximum_setup_slack | Reports a violation for timing paths that have a setup slack below the value of this parameter. | double | 0.0 | ||
| to_clock_filter | Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. | string | * | ||
| minimum_number_of_adders | Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. | integer | 3 | ||
| minimum_number_of_soft_mult_chains | Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. | integer | 2 |
Recommendation
If there are no more global resources available and the number of clocks cannot be reduced, the number of fan-outs should be reduced to prevent having to route as far which will decrease the skew present. Otherwise the associated node on the clock path should be promoted to global routing using the QSF "set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to <instance_name>".
Severity
Medium
Tags
| Tag | Description |
|---|---|
| global-signal | Design rule checks related to global signals. |
| clock-skew | Design rule checks related to clock skew. |
Device Family
- Intel®Stratix® 10
- Intel®Agilex™
- Intel®Arria® 10
- Intel®Cyclone® 10 GX