LNT-30018: Design Contains Delay Chains

Description

Delay chains are one or more consecutive nodes that act as a buffer for creating intentional delay.

Figure 1. Delay Chain Examples

Delay chains often result from asynchronous design practices and can cause problems, including an increase in a design's sensitivity to operating conditions, and a decrease in a design's reliability. In addition, using a delay chain is unnecessary in purely synchronous circuits that use dedicated clocks in the Intel Quartus Prime Pro Edition software.

This rule detects delay chains implemented in the logic cell only. This rule does not detect delay chains in I/O portions of the device.

Note:
  • Violations of this rule can occur when a design contains pre-built Intel FPGA IP with parameter settings that cause an EDA synthesis tool to retain all unused logic elements from the design during synthesis. When Intel FPGA IP functions are the cause of violations, the design is still synchronous and the unused logic elements do not cause problems in the design.
  • Violations can also occur where a delay chain exists on the clock or reset path, but not when a delay chain is used on the data path.

Recommendation

Do not include delay chains in your design.

Severity

Low

Tags

Tag Description
logic-levels Design rule checks which flag potentially problematic amounts of logic on a timing path.

Device Family

  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX