LNT-30011: Design Contains Combinational Loops

Description

A combinational loop is combinational logic that drives itself without synchronization by a register.

Figure 1. Combinational Loop

A particular occurrence of combinational loops involves feeding the output of a flip-flop back to an asynchronous pin (clear, preset, and load) of the same flip-flop through some combinational logic.

Figure 2. Flip-Flop.. The following figure shows a combinational path exists between an asynchronous pin and the output of the flip-flop, creating a loop.

Recommendation

Restructure the netlist to break the combinational loop, as these loops can cause significant stability and reliability problems in a design. For example, due to the following reasons, the combinational loop after fitting may not function as originally intended in the design:

  • The behavior of a combinational loop often depends on the relative propagation delays of the combinational loop's logic.
  • Design tools experience difficulties when handling combinational loops.

Severity

High

Tags

Tag Description
nonstandard-timing Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic.

Device Family

  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX