CLK-30002: Clock Source Driving Non-clock Pins
Description
This rule detects issues that are not reported by more specific clock structures, such as:
- Multiplexed clocks
- Clock dividers that are not based on synchronous counters or state-machines
- D-latches based on the asynchronous load feature
When a design contains clock signal sources that connect to ports other than clock ports, the design is asynchronous and has associated issues and challenges of asynchronous designs.
Recommendation
The clock signal source in a design should drive only clock input ports of registers. Correct any unintended connectivity.
Severity
Medium
Tags
Tag | Description |
---|---|
nonstandard-timing | Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic. |
Device Family
- Intel®Arria® 10
- Intel®Cyclone® 10 GX