variable Definition

A name that represents a node. In AHDL, a variable can also represent a state machine or an instance of a primitive, Intel^® FPGA IP, or macrofunction and is declared in the Variable Section. In VHDL, variables have a single current value, and are declared and used only in processes and subprograms. A VHDL variable is declared with a Variable Declaration; the value of a variable can be modified with a Variable Assignment Statement.