Exploration Page (Design Space Explorer II)

Exploration Name

Name that you give to the DSE II session.

Compilation Type

Type of compilation to perform. You can choose between Full Compilation, Fitting and timing analysis and Fitting, timing analysis, and assembler.

Exploration Points

Option Description
Exploration Points
Single compilation Allows you to set up a single compilation in a remote location and monitor from the local computer.
Design Exploration Allows you to generate many compilations in remote machines, each of them with different parameters or settings.
Exploration Options
Exploration flow to use. The following options are available:
Seed Sweep Only

Directs DSE II to vary only the seed setting in the Fitter, using the seed values you specified in Seeds.

The Fitter uses the seed during the initial placement configuration and when optimizing the design to meet the timing requirements, including fMAX. Because each different seed value will result in a somewhat different fit, you can try different seeds to attempt to obtain superior fitting results.
Note: The seeds that lead to the best fits for a design may change if the design changes. Also, changing the seed not always results in a better fit; therefore, you should specify a seed only if the Fitter is not meeting timing requirements by a small amount
.
All Compilation Strategies Optimizes synthesis for balanced implementation that respects timing constraints. When you specify this option, te number of runs is 5x the number of seeds (+ optional base compile).
High Performance Effort The Compiler increases the timing optimization effort during placement and routing, and enables timing-related Physical Synthesis optimizations (per register optimization settings). Each additional optimization can increase compilation time.
Superior Performance with Maximum Placement Effort Enables the same Compiler optimizations as Superior Performance, with additional placement optimization effort.
High Performance with Optimized Placement Effort Optimize synthesis for speed performance, , with additional placement optimization effort.
Superior Performance with High Placement Effort Optimize synthesis for speed performance, with additional placement optimization effort.
Superior Performance with Optimized Placement Effort Optimize synthesis for speed performance. Aggressive effort increases Fitter runtime and device resource use.
Superior Performance Enables the same Compiler optimizations as High Performance Effort, and adds more optimizations during Analysis & Synthesis to maximize design performance with a potential increase to logic area. If design utilization is already very high, this option may lead to difficulty in fitting, which can also negatively affect overall optimization quality.
High Performance with Maximum Placement Effort Optimize synthesis for speed performance, with additional placement optimization effort.
Maximum Placement Effort Makes the maximum effort to implement placement, at the expsense of additional placement optimization time.
Extra Effort on Retiming Retimer makes extra effort to retime registers for the best performance.
High Placement Effort Makes high effort to implement placement, at the expsense of additional placement optimization time.
High Power Effort The Compiler makes high effort to optimize synthesis for low power. High Power Effort increases synthesis run time.
Aggressive Power Makes aggressive effort to optimize synthesis for low power. The Compiler further reduces the routing usage of signals with the highest specified or estimated toggle rates, saving additional dynamic power but potentially affecting performance.
High Placement Routability Effort The Compiler makes high effort to route the design at the potential expense of design area, performance, and compilation time. The Compiler spends additional time reducing routing utilization, which can improve routability and also saves dynamic power.
Optimize Netlist for Routability The Compiler implements netlist modifications to increase routability at the possible expense of performance.
High Packing Routability Effort The Compiler makes high effort to route the design at the potential expense of design area, performance, and compilation time. The Compiler spends additional time packing registers, which can improve routability and also saves dynamic power.
Aggressive Area The Compiler makes aggressive effort to reduce the device area required to implement the design at the potential expense of design performance.
Aggressive Compile Time Reduces the compile time required to implement the design with reduced effort and fewer performance optimizations. This option also disables some detailed reporting functions.
Note: Turning on Aggressive Compile Time enables Intel® Quartus® Prime Settings File (.qsf) settings which cannot be overridden by other .qsf settings.
Seeds
Specifies the random seeds that the compilation must use. Choose between:
Create Number of seeds to sweep as part of the exploration space. The DSE II uses consecutive seeds
Specify List of seeds that the DSE II must use
Skip base exploration points If you turn this option on, the DSE II generates compilation only for non-default settings.

Design File Setup

Option Description
Create design archive from Intel® Quartus® Prime project Each compilation generates a qar file.
Discover and include source files missing from project settings Activate auto discover file feature. If enabled, the software runs analysis and elaboration if it has not been run to discover source files.

If the QSF file already contains all design files, you can turn off this option to reduce runtime and memory consumption.
Use existing design archive (.qar) Each compilation imports the qar file from the local machine.

Limits

Select one of the following options:

Option Description
Stop after any exploration meets timing Exploration stops when a compilation meets the timing goals.
Limit compilation for each exploration point to Defines a time limit for each compilation.

Results

Option Description
Select results to save
Specify what result files to keep after an exploration point completes. The alternatives are:
all
qar
best_qar
sof
sof_qar
reports_only

DSE Server Settings

For LSF farms, you can use a remote machine to generate compilations and gather results. With this configuration, the local machine is free to disconnect from the network during the exploration process, and can connect later to check the results.

To retrieve the exploration results we need the IP remote machine to contact. We achieve this by having remote machine register with the local machine.

Option Description
Host IP of the local machine
Port Port that the local machine is using
Registration Host IP of the machine that generates the compilations
Registration Port Port that the registration host is using

Advanced

Option Description
Specify exploration points without compiling Allows you to compile your design at a later point in time.
Maximum number of parallel compilations Number of CPUs each compiler must use.
Maximum number of CPUs Maximum CPUs that the DSE can use
Quality of Fit formula Name of the Python script that calculates a custom Quality of Fit value. This path is relative to the project directory