DFFE Primitive
The DFFE primitive allows you to specify a D-type flipflop with clock enable.
Note: When the ENA (clock enable) input is high, the flipflop passes a
signal from D to Q. When the ENA
input is low, the state of Q is maintained, regardless of the
D input.
For devices that do not support clock enable, logic synthesis generates logic equations representing flipflops with clock enables. These logic equations correctly emulate the logic specified in the project.
Note: For information about Intel® Quartus® Prime primitive instantiation, go to Using a Intel® Quartus® Prime
Logic Function.