Input Ports
Port Name |
Required |
Description |
Comments |
---|---|---|---|
data[] |
Yes |
Data inputs/bit enables for the T flipflops. Data input during aload or sload. |
Input port LPM_WIDTH wide. |
clock |
Yes |
Positive-edge-triggered clock. |
|
enable |
No |
Clock enable input. Enables all synchronous activities. |
If omitted, the default value is enabled (1). |
sclr |
No |
Synchronous clear input. Clears the T flipflop on the next active clock edge. |
If omitted, the default value is 0. If both sset and sclr are used and both are asserted, sclr is used. |
sset |
No |
Synchronous set input. Sets the T flipflop on the next active Clock edge. |
If omitted, the default value is 0. Sets q[] outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q to all 1's. If both sset and sclr are used and both are asserted, sclr is dominant. |
sload |
No |
Synchronous load input. Loads the T-type flipflops with the value on the data input on the next active Clock edge. |
If omitted, the default value is 0. If sload is used, data must be used. For load operation, sload must be high (1) and enable must be high or unconnected. |
aclr |
No |
Asynchronous clear input. |
If omitted, the default value is 0. If both aset and aclr are used and both are asserted, aclr is used. |
aset |
No |
Asynchronous set input. |
If omitted, the default value is 0. Sets q[] outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1s. If both sset and sclr are used and both are asserted, sclr is used. |
aload |
No |
Asynchronous load input. Asynchronously loads the T flipflops with the value on the data input. |
If omitted, the default value is 0. If aload is used, data must be used. |