Truth Table/Functionality

The lpm_clshift Intel^® FPGA IP acts like a barrel shifter. It contains entirely combinational logic.

Overflow occurs when the shifted result exceeds the precision of the result bus. For "LOGICAL" values, overflow occurs when any 1 has been shifted out. For "ARITHMETIC" values, overflow occurs when a significant digit is shifted into or past the sign bit. Underflow occurs when the shifted result contains no significant digits.

Operation of the LOGICAL shifter is illustrated in the following example, in which LPM_WIDTH = 4:

Inputs			Output
direction	`distance[1..0]`	`data[3..0]`	overflow	`result[3..0]`	`underflow`
X	0	`dcba`	0	`dcba`	0
0	1	`dcba`	`d`	`cba`0	0
0	2	`dcba`	`d` # `c`	`ba`00	0
0	3	`dcba`	`d` # `c` # `b`	`a`000	0
1	1	`dcba`	0	0`dcb`	!`d` & !`c` & !`b` & `a`
1	2	`dcba`	0	00`dc`	!`d` & !`c` & (`b` # `a`)
1	3	`dcba`	0	000`d`	!`d` & (`c` # `b` # `a`)

Operation of the ARITHMETIC shifter is illustrated in the following example, in which LPM_WIDTH = 4:

Inputs			Output
`direction`	`distance[1..0]`	`data[3..0]`	`overflow`	`result[3..0]`	`underflow`
X	0	`dcba`	0	`dcba`	0
0	1	0`cba`	`c`	`cba0`	0
0	1	1`cba`	!`c`	`cba0`	0
0	2	0`cba`	`c` # `b`	`ba`00	0
0	2	1`cba`	`c`! # `b`!	`ba`00	0
0	3	0`cba`	`c` # `b` # `a`	`a`000	0
0	3	1`cba`	!`c` # !`b` # !`a`	`a`000	0
1	1	0`cba`	0	00`cb`	!`c` & !`b` & `a`
1	1	1`cba`	0	11`cb`	`c` & `b` & !`a`
1	2	0`cba`	0	000`c`	!`c` & (`b` # `a`)
1	2	1`cba`	0	111`c`	`c` & (!`b` # !`a`)
1	3	0`cba`	0	0000	(`c` # `b` # `a`)
1	3	1`cba`	0	1111	(!`c` # !`b` # !`a`)

Operation of the ROTATE shifter is illustrated in the following example, in which LPM_WIDTH = 4:

Inputs			Output
`direction`	`distance[`1`.`.0`]`	`data[`3`.`.0`]`	`result[`3`.`.0`]`
X	0	`dcba`	`dcba`
0	1	`dcba`	`cbad`
0	2	`dcba`	`badc`
0	3	`dcba`	`adcb`
1	1	`dcba`	`adcb`
1	2	`dcba`	`badc`
1	3	`dcba`	`cbad`