Check Timing Command
Generates the Check Timing report that lists the following possible problems with constraints or conditions in the design:
Check |
Description |
---|---|
no_clock |
Verifies that ports or registers determined to be clocks have a clock assigned to them, and reports the number of registers that do not have at least one clock driving the clock pin. |
multiple_clock |
Reports the number of registers that have more than one clock signal driving the clock pin. |
pos_neg_clock_domain |
Reports the number of registers clocked by both the rising and falling edges of the same clock. |
generated_clock |
Reports the number of valid generated clocks. Generated clocks must have a source that is clocked by a valid source clock. Also, the generated clock and the source clock must not depend on each other in a loop (that is, clk1 cannot have clk2 as a source if clk2 already uses clk1 as a source). |
virtual_clock |
Reports the number of virtual clocks that are not referenced by the set_input_delay and set_output_delay Synopsys® Design Constraints (SDC) commands, meaning that they are unused. |
no_input_delay |
Reports the number of input ports that are not determined to be clocks and do not have an input delay constraint. |
no_output_delay |
Reports the number of output ports that do not have an output delay constraint. |
partial_input_delay |
Reports the number of input delays that are not complete but include one or more of the following:rise-min, fall-min, rise-max, or fall-max. |
partial_output_delay |
Reports the number of output delays that are not complete but include one or more of the following: rise-min, fall-min, rise-max, or fall-max. |
io_min_max_delay_consistency |
Verifies and reports whether or not min delay values specified by set_input_delay or set_output_delay assignments are less than max delay values. |
reference_pin |
Reports the number of invalid reference pins specified in the set_input_delay and set_output_delay SDC commands that use the - reference_pin option. A reference pin is valid if the -clock option specified in the same set_input_delay or set_output_delay command matches the clock that is in the direct fan-in of the reference pin. To be considered part of the direct fan-in of the reference pin, there must be no keepers or clocks between the clock and reference pin. |
generated_io_delay |
Reports the number of instances of set_input_delay or set_output_delay SDC commands where the -clock option is internally generated, and the command does not use the - reference_pin or -source_latency_included options. |
latency_override |
Reports the number of occurrences where clock latency set on a port or pin overrides the more clock latency set on a clock. You can set clock latency on a clock, where the latency applies to all keepers clocked by the clock. You can also set clock latency on a port or pin, where the latency applies to registers in the fan-out of the port or pin. |
partial_multicycle |
Reports the number of setup multicycle assignments where there are not corresponding explicitly-set hold multicycle assignments. |
multicycle_consistency |
Reports all the multicycle cases where a setup multicycle assignment does not equal one greater than the corresponding hold multicycle assignment. Hold multicycle assignments are typically one cycle less than setup multicycle assignments. |
loops |
Reports the number of strongly connected components in the timing netlist. These loops prevent the Timing Analyzer from properly analyzing a design. Provides a warning if loops exist that are marked so they are not traversed. |
latches |
Reports the number of latches in the design, and provides a warning if any exist. The Timing Analyzer cannot properly analyze latches. |
pll_cross_check |
Reports the number of clocks assigned to a Phase-Locked Loop (PLL) Definition based on the PLL settings defined in the design file. This check reports inconsistent settings or an unmatched number of clocks associated with the PLL. |
uncertainty |
Reports the number of clock transfers in the design where the set_clock_uncertainty constraint is not set between the two clocks. This report also checks if the set_clock_uncertainty constraints you made have less than recommended clock uncertainty values. |
partial_min_max_delay |
Verifies that each minimum or maximum delay assignment has a corresponding maximum or minimum delay assignment. |
clock_assignments_on_output_ports |
Reports all clock assignments applied to output ports. |
input_delay_assigned_to_clock |
Verifies that no input delay value is set for a clock. Input delays set on clock ports are ignored because clock-as-data analysis takes precedence. |
Scripting Information |
Keyword: check_timing Settings: panel_name "CheckTiming" |