Filter

Specifies the current Intel-provided or user-defined filter. The Intel® Quartus® Prime software includes the following non-editable, default filters. You can use these filters to perform a node name search, or you can create a new filter using any of the Intel-provided filters settings as the initial settings.

  • Design Entry (all names)—Finds all user-entered names in your design file(s).
  • Pins: assigned—Finds all assigned pin names in your design file(s).
  • Pins: unassigned—Finds all unassigned pin names in your design file(s).
  • Pins: input—Finds all input pin names in your design file(s).
  • Pins: output—Finds all output pin names in your design file(s).
  • Pins: bidirectional—Finds all bidirectional pin names in your design file(s).
  • Pins: virtual—Finds all virtual pin names.
  • Pins: all—Finds all pin names in your design file(s).
  • Pins: all & Registers: post-fitting—Finds all pin and user-entered register names in your design file(s) that survived physical synthesis and fitting.
  • Ports: partition—Finds all port names in your design file(s) that belong to the selected partition.
  • Entity instance: pre-synthesis—Finds all entity names in your design file(s) after design elaboration, but before physical synthesis does any synthesis optimizations.
  • Registers: pre-synthesis—Finds all user-entered register names contained in the design after design elaboration, but before physical synthesis does any synthesis optimizations.
  • Registers: post-fitting—Finds all user-entered register names in your design file(s) that survived physical synthesis and fitting.
  • Post-synthesis—Finds all port names in your design file(s) that survived physical synthesis.
  • Post-Compilation—Finds all user-entered and compiler-generated names that do not have location assignments and survived fitting.
  • Signal Tap: pre-synthesis—Finds all internal device nodes in the pre-synthesis netlist that can be analyzed by the Signal Tap Logic Analyzer.
  • Signal Tap: post-fitting—Finds all internal device nodes in the post-fitting netlist that can be analyzed by the Signal Tap Logic Analyzer.
  • Signal Probe—Finds all Signal Probe device nodes in the post-fitting netlist.