Parameters
You can pipeline a design by connecting the clock input and specifying the number of clock cycles of latency with the LPM_PIPELINE parameter. You may also be able to increase the performance by controlling the placement of the pipeline registered stages with the PIPELINE_DELAY parameter.
| Parameter | Type | Required | Description |
|---|---|---|---|
| WIDTH_N | Integer | Yes | Width of the numerator[] port. |
| WIDTH_D | Integer | Yes | Width of the denominator[] port. |
| WIDTH_Q | Integer | Yes | Width of the quotient[] port, usually equal to WIDTH_N. If WIDTH_D_MIN is used, this value must be specified as WIDTH_N-WIDTH_D_MIN+1. |
| WIDTH_R | Integer | Yes | Width of the remainder[] port, which must be specified as MIN(WIDTH_N, WIDTH_D). |
| WIDTH_D_MIN | Integer | No | Minimum width of the denominator port, if known. 1<=WIDTH_D_MIN<=MIN(WIDTH_N, WIDTH_D). Example: If the denominator port is known to be always greater than or equal to H"10", WIDTH_D_MIN can be set to 5. The default value is 1. |
| LPM_PIPELINE | Integer | No | Specifies the number of Clock cycles of latency associated with the quotient[] and remainder[] outputs. A value of zero (0) indicates that no latency exists, and that a purely combinational function will be instantiated. If omitted, the default is 0 (non-pipelined). You cannot specify a value for the LPM_PIPELINE parameter that is higher than WIDTH_Q. |
| PIPELINE_DELAY | Integer | No | Shifts the placement of the pipeline registered stages. By default, WIDTH_Q/2 starts at the middle stage. Specify 0 to start at the last stage. Specify WIDTH_Q-1 to start at the first stage. The default value is WIDTH_Q/2. |