Input Ports

aclr

No

Asynchronous clear for pipelined usage.

The pipeline initializes to an undefined (X) logic level. The aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to the clock signal. The outputs are a consistent, but non-zero value.

clock

No

Clock for pipelined usage.

The clock port provides pipelined operation for the lpm_mult function. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected.

data[]

Yes

Multiplicand.

Input port [DATA_WIDTH-1..0] wide.

ena

No

Clock enable for pipelined usage.

If omitted, the default is 1.