TMC-20201: Paths Failing Setup Analysis with High Clock Skew
Description
Violations of this rule identify paths with a "clock-skew-only slack" below the maximum_setup_slack threshold parameter.
Timing paths may fail setup analysis without any delay contributions from cell delay or interconnect delay. If those components are removed from the overall slack, the remaining slack is the path's clock skew, as well as the combination of its clock relationship, endpoint microparameters, SDC constraints, and other such requirements. These components together constitute a path's "clock-skew-only slack." A negative "clock-skew-only slack" implies that the clock skew between the path's endpoints must be reduced or its requirements must be relaxed to meet timing.
For example, consider a path with a combined μtco, μtsu, and clock skew that exceeds the target clock period. Such a path is likely to fail setup analysis, and as such its "clock-skew-only slack" is negative. Reduce clock skew between the path's endpoints or relax its setup requirements to close timing.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| maximum_setup_slack | Reports a violation for timing paths that have a setup slack below the value of this parameter. | double | 0.0 | ||
| to_clock_filter | Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. | string | * | ||
| minimum_number_of_adders | Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. | integer | 3 | ||
| minimum_number_of_soft_mult_chains | Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. | integer | 2 |
Recommendation
Restructure or re-constrain the path to increase its intrinsic margin or reduce its clock skew using any of the following:
- Ensure the launch and latch clocks are routed globally.
- Resize clock regions.
- Redesign cross-clock transfers.
- Adjust SDC constraints to relax the path's setup constraint.
- If the launch and latch clocks are different, ensure their relationship is properly constrained.
- If the path's endpoints involve DSP, RAM, or I/O blocks, ensure that those blocks are sufficiently registered (See the "RAM Summary" and "DSP Register Packing Details" Fitter report tables for more information).
Severity
Medium
Tags
| Tag | Description |
|---|---|
| intrinsic-margin |
Device Family
- Intel® Stratix® 10
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX