TMC-20052: Inferred Latch Count Check
Description
Design Assistant detected one or more inferred latches. Inferred latches are often unintended in FPGA designs.
Recommendation
Remove any unintended inferred latches from the design.
Severity
Low
Tags
| Tag | Description |
|---|---|
| nonstandard-timing | |
| latch |
Device Family
- Intel® Agilex™
- Intel® Stratix® 10
- Intel® Arria® 10
- Intel® Cyclone® 10 GX