CDC-50006: CDC Bus Constructed with Unsynchronized Registers
Description
Violations of this rule identify multi-bit unsynchronized transfers that form a CDC bus.
Recommendation
If the bus does not transfer Gray-coded data, change its implementation to incorporate a control signal since synchronizer chains are not sufficient to ensure that all bits of the bus latch on the same clock cycle.
If the bus transfers Gray-coded data, protect it using synchronizer chains. To do this, ensure that the destination of each bit forms a chain of two or more registers, with each register in the same clock domain as the destination of the bus transfer, and with no combinational logic between any of the registers in any of the chains. Also, ensure that there is no combinational logic on the bus transfer, and that the chains following each bit all contain the same number of registers.
Severity
High
Tags
Tag | Description |
---|---|
synchronizer | |
cdc-bus |
Device Family
- Intel® Cyclone® 10 GX
- Intel® Arria® 10
- Intel® Stratix® 10
- Intel® Agilex™