CDC-50003: CE-Type CDC Bus with Insufficient Constraints

Description

Violations of this rule identify a CDC bus synchronized by DFFE (D Flip-Flop with Enable) registers with insufficient timing constraints. Without proper constraints, all bits of such a bus may not latch on the same clock cycle.

Recommendation

Apply an instance assignment of Synchronization Register Chain Length = 1 on the head of a CE-type CDC bus to prevent downstream registers from being treated as a synchronizer chain. Next, apply a set_max_skew constraint on the bits of the bus to ensure that all bits latch on the same clock cycle. The value of the skew constraint must be equal to or lower than either the source or destination clock period, whichever is lower. This can be accomplished with the following constraint:

set_max_skew -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier $value_between_0_and_1 -from [get_registers $source_registers] -to [get_registers $destination_registers]

Also, apply a set_net_delay constraint on the bits of the bus to limit their allowable delay. The value of the net delay constraint must be equal to or lower than the destination clock period. This can be accomplished with the following constraint:

set_net_delay -max -get_value_from_clock_period dst_clock_period -value_multiplier $value_between_0_and_1 -from [get_registers $source_registers] -to [get_registers $destination_registers]

Figure 1. Example Transfer to a Multi-Bit Register Controlled by a Clock Enable Pin. In the following figure, the enable signal is synchronized, but requires a max skew constraint on the n-bit data transfer.

Severity

High

Tags

Tag Description
cdc-bus  

Device Family

  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10
  • Intel® Stratix® 10
  • Intel® Agilex™