Reanalyze HDL Files Command (File Menu) (Platform Designer Component Editor)
You access this command in the Platform Designer Component Ediot by clicking .
Analyzes the design files of the component by running Intel® Quartus® Prime Analysis and Elaboration. The Component Editor analyzes signals and parameters declared for all modules in the file. If any of the design files contain syntax errors, a message appears describing the problems. After successful analysis of the design files, Platform Designer updates the list of signals and parameters for the component.
Important: Important: When importing an HDL file
into the Component Editor, any parameter definitions that are
dependent upon other defined parameters cause an error. For example
the following DEPTH
parameter, though legal Verilog HDL syntax in the Intel® Quartus® Prime
software, causes an error when imported into the Component
Editor: parameter WIDTH =
32; parameter DEPTH =
((WIDTH == 32) ? 8 : 16); To avoid this error, use localparam for
the dependent parameter instead: parameter WIDTH =
32; localparam DEPTH =
((WIDTH == 32)?8:16);