Force Merging of PLLs logic option

A logic option that directs the Fitter to merge the two specified PLLs.

The two PLLs merged with this option must be compatible PLLs driven by the same clock source.

This option is available for supported device (Arria^® II, Cyclone^® III, Cyclone^® IV, Stratix^® III, and Stratix^® IV) families.