Module Instantiation Using Mixed Languages
To instantiate a Verilog module inside a VHDL entity, you must first declare a component that models the interface of the Verilog HDL module. The component should have the same port names and port ranges as the Verilog HDL module declaration.
- If the port names do not match, the Intel® Quartus® Prime software issues an error.
- If the port ranges do not match, the Intel® Quartus® Prime software issues a warning and connects individual bits in the port by name.
In the this example, the VHDL component for the Verilog HDL module sub declares port A with the range 1 to 4, which does not match the range of port a in sub.
From Verilog HDL:
module sub(input a[5:2],...)"...
From VHDL, the prototype of sub looks like:
COMPONENT sub PORT ( A : IN STD_LOGIC_VECTOR (1 TO 4); ... ); END COMPONENT;
The Intel® Quartus® Prime software will connect the component and module ports as follows:
Verilog HDL Pin |
VHDL Port |
---|---|
No match |
A[1] |
a[2] |
A[2] |
a[3] |
A[3] |
a[4] |
A[4] |
a[5] |
No match |